During wafer fabrication of semiconductor devices, various surfaces are formed. Many of such surfaces do not have uniform height, and therefore, the wafer thickness is also non-uniform. For example, as is shown in FIG. 1A, the height of the boro-phosphosilicate glass (BPSG) layer 12 of the wafer section 10, does not have the same height at areas 14, 16 and 18. Further, surfaces may have defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. For various fabrication processes to be performed, such as lithography and etching, height non-uniformities and defects at the surface of the wafer must be reduced or eliminated. Various planarization techniques are available to provide such reduction and/or elimination. One such planarization technique includes chemical-mechanical polishing (CMP).
The method of CMP is used to achieve a planar surface over the entire chip and wafer, sometimes referred to as "global planarity." Typically, the process of CMP involves a rotating wafer holder that holds a wafer. A slurry is applied to a rotating table or platen which has a polishing pad thereon. The polishing pad is applied to the wafer at a certain pressure to perform the planarization. In some CMP processes, the wafer holder may not rotate, the table or platen may not rotate and/or the platen may be moved in a linear motion as opposed to rotating. There are numerous types of planarization units available which perform the process in different manners.
In many circumstances, even after CMP has been performed, surface nonuniformities of the wafer are present. For example, because of different rotational speeds of the process at the center of the wafer as opposed to the edge of the wafer and different rotational speeds of the rotating table at the center and at the rotating table's periphery, the rate of removal tends to be different across the wafer surface. For example, the removal rate at the edge of the wafer may be higher than at the center of the wafer. Further, for example, the slurry may not be adequately transported to the entire contact area between the wafer and the pad such that further rate of removal differences are created. Slurry transport to the center of the wafer may also be inadequate when the surface is, or becomes as a result of CMP, substantially planar and further planarization is to be performed. This is because no gaps or nonuniformities are available to assist the transport of the slurry to the middle of the contact area.
Nonuniformity of the wafer surface, even after CMP, may be problematic. For example, such nonuniformity may lead to patterning or photolithography problems. Further, such nonuniformity may result in etching at undesirable depths on the wafer surface.
Nonionic surfactants have been added to slurries during CMP in an attempt to enhance uniformity of the material removed from the wafer surface. For example, as described in "Uniformity of Removal Rate in the CMP of Silicon Dioxide Films," by K. Achuthan, et al., DUMIC Conference, Feb. 21-22, 1995, polyethylene oxide (20) stearyl ether (PEO(20)) and polyethylene oxide (10) stearyl ether (PEO(10)) were added to slurries during planarization by CMP. However, the addition of such surfactants reduced the removal rate of the surface material significantly. Reduction of the removal rate is undesirable as it decreases the machine through rate. Further, some surfactants may result in a contaminated surface following cleaning of the surface after CMP is performed.
For the above reasons, improvements in the CMP process are needed to provide adequate uniformity of the planarized surfaces in the wafer fabrication of semiconductor devices. The present invention as described below provides such improvements and overcomes the problems described above and those problems which will become apparent to one skilled in the art from the detailed description provided below.